The present subject matter generally concerns arrays and related methodology. More particularly, the present subject matter concerns a multilayer components (for example, such as varistors) with interdigitated electrode layer portions configured so as to variously provide signal filtering characteristics, over-voltage transient suppression capabilities, and land grid array (LGA) terminations.
Integrated circuits (ICs) have been implemented for some time, but many specific features of these ICs affect the design criteria for electronic components and corresponding procedures for mounting such components. With increased functionality of integrated circuit components, the design of electronic components must become increasingly more efficient. The miniaturization of electronic components is a continuing trend in the electronics industry, and it is of particular importance to design parts that are sufficiently small, yet simultaneously characterized by high operating quality. Components are desired that are small in size and that have reliable performance characteristics, yet can also be manufactured at relatively low costs.
Component miniaturization enables higher density mounting on circuit boards or other foundations. Thus, the spacing between components is also a limiting factor in present circuit designs. Since spacing is such a critical design characteristic, the size and location of termination means or elements for IC components is also a significant design characteristic.
One specific electronic component that has been used in IC applications is the decoupling capacitor. Decoupling capacitors are often used to manage electrical noise problems that occur in circuit applications. As such, one of their functions is to operate as a filter. Dramatic increases in packing density of integrated circuits require advancements in decoupling capacitor technology. It has been found that one way to achieve improved performance of decoupling capacitors and at the same time allow for increased packaging density is to provide improved filtering characteristics and, at the same time, incorporate additional functionality in the form of transient suppression.
Several design aspects have been implemented in prior decoupling capacitors to reduce self and mutual inductance. For example, it has been shown that reducing the current path through such devices will lower self-inductance. Since the current often has to travel the entire length of the capacitor, termination on the longer ends of the structure will reduce the current path. If the current in adjacent capacitor electrodes flows in opposite directions it will reduce the mutual inductance in a capacitor. Multiple terminations as utilized in interdigitated capacitor technology lower the inductance value.
Another approach to lowering the equivalent series inductance (ESL) of a decoupling capacitor is to minimize interconnect induction that results from termination configurations and mounting systems. Typical termination schemes incorporate long traces to the capacitor electrode pads.
Examples of various aspects and alternative embodiments in the field of integrated circuits (ICs), and particularly for example, regarding multilayer decoupling capacitors, have been implemented for some time. Some exemplary specific features and aspects of ICs and associated electronic components and corresponding procedures for mounting such components include as follows. U.S. Pat. No. 4,831,494 (Arnold, et al.) is entitled “Multilayer capacitor” and discloses what it describes as a multilayer capacitor consisting of a plurality of laminae with each of the laminae including a conductive plate portion and a non-conductive sheet portion. The conductive plate portion has at least one tab projecting to at least one edge of the conductive plate portion with the maximum number of tabs per conductive plate portion being limited to avoid excessive lateral congestion. The laminae are divided into different groups with the laminae from each group having the same number and location of tabs and with the laminae from different groups differing by at least the location of the tabs. The laminae are interleaved so that: (a) a lamina from one group alternates with a lamina from a different group, (b) the conductive plate portion of each lamina is in contact with the non-conductive sheet portion of each adjacent lamina, (c) the tabs are at a common edge of each lamina so that the tabs of the interleaved laminae form rows of tabs, and (d) the tabs from adjacent laminae are not in registry with each other. The capacitor finally includes islands of metallurgy joining selected groups of tabs in each row such that each of the islands covers a portion of each row of tabs.
U.S. Pat. No. 5,799,379 (Galvagni, et al.) is entitled “Method of manufacturing a decoupling capacitor structure” and discloses what it describes as a capacitor structure described as having a plurality of dielectric materials located so that each dielectric material is in parallel between capacitor plates. The capacitor value of this structure is preset, therefore, for operation electrically at different specific temperatures. The description gives a specific stacked arrangement for the various dielectric materials in which this capacitor can be formed, as one example of that to which it is adaptable.
U.S. Pat. No. 6,757,152 (Galvaqni, et al.) is entitled “Cascade capacitor” and discloses what it describes as multi-layer and cascade capacitors for use in high frequency applications and other environments. Such subject capacitor may have multiple capacitor components or aspects thereof in an integrated package. Such components may include, for example, thin film BGA components, interdigitated capacitor (IDC) configurations, double-layer electrochemical capacitors, surface mount tantalum products, multilayer capacitors, single layer capacitors, and others. Exemplary embodiments of such subject matter preferably encompass at least certain aspects of thin film BGA techniques and/or IDC-style configurations. Features for attachment and interconnection are provided that facilitate low ESL while maintaining a given capacitance value. Additional advantages include low ESR and decoupling performance over a broad band of operational frequencies. More particularly, such disclosed technology provides for exemplary capacitors that may function over a frequency range from kilohertz up to several gigahertz, and that may also be characterized by a wide range of capacitance values. An additionally disclosed feature of such subject matter is to incorporate dielectric layers of varied thicknesses to broaden the resonancy curve associated with a particular configuration.
U.S. Pat. No. 7,016,175 (MacNeal et al.) is entitled “Window via capacitor” and discloses what it describes as a window via capacitor which comprises a stacked multilayer configuration of at least one bottom layer, a plurality of first and second layers, a transition layer and a cover layer. Each first and second layer is preferably characterized by a sheet of dielectric material with a respective first or second electrode plate provided thereon. Adjacent first and second electrode plates form opposing active capacitor plates in the multilayer configuration. Portions of each first and second electrode plate extend to and are exposed on selected periphery side portions. Electrode portions of each transition layer are aligned in respective similar locations to the first and second electrode plates such that peripheral terminations can connect selected electrode portions of a first polarity together and selected portions of the opposing polarity together. Solder balls may also be applied to window vias to yield a capacitor compatible with BGA mounting technology.
U.S. Pat. No. 4,039,997 (Huang. et al.) is entitled “Resistance material and resistor made therefrom” and discloses what it describes as a vitreous enamel resistance material comprising a mixture of a vitreous glass frit and fine particles of a metal silicide of the transition elements of Groups IV, V and VI of the periodic chart. The metal silicide may be of molybdenum disilicide (MoSi.sub.2), tungsten disilicide (WSi.sub.2), vanadium disilicide (VSi.sub.2), titanium disilicide (TiSi.sub.2), zirconium disilicide (ZrSi.sub.2), chromium disilicide (CrSi.sub.2) or tantalum disilicide (TaSi.sub.2). The ingredients of the vitreous enamel resistance material are present in the proportion of, by weight, 25 to 90% glass frit and 75 to 10% metal silicide. An electrical resistor is made with the vitreous enamel resistor material of the present subject matter by coating a ceramic substrate with the vitreous enamel resistance material and firing the coated substrate at a temperature sufficient to melt the glass frit of the vitreous enamel resistance material. Upon cooling, the glass hardens so that the resultant resistor comprises the substrate having on the surface thereof a film of glass with the metal silicide particles embedded in and dispersed throughout the glass film.
U.S. Pat. No. 4,286,251 (Howell) is entitled “Vitreous enamel resistor and method of making the same” and discloses what it describes as a vitreous enamel resistor, and method of making the same comprising the steps of applying to the surface of a substrate and firing a mixture of glass frit and particles of a precious metal oxide such as iridium oxide, ruthenium oxide, and mixtures thereof. The mixture is fired in a neutral, inert, or reducing atmosphere for a time and at a temperature resulting in a controlled partial dissociation of the oxide and softening of the glass frit. When cooled, a resistor is provided having a glass film with conductive particles therein strongly bonded to the substrate. The resistor produced can be terminated by the use of electroless plating.
The disclosures of the foregoing United States patents are hereby fully incorporated into this application for all purposes by reference thereto. While examples of various aspects and alternative embodiments are known in the field of multilayer decoupling capacitors, no one design is known that generally encompasses all of the above-referenced preferred characteristics.